The invention relates to integrated circuits with intrinsic protection both against electrostatic discharges and also against permanent overloads, such as reversals of polarity or overvoltages.
The disclosed inventions can be used to provide integrated circuits with very wide-ranging protection against deliberate destruction wrought with malicious or fraudulent intent and accidental destruction prompted by static electricity, lightning and magnetic storms or through mishandling or human error (resulting in reversal of polarity, overvoltage etc.).
The widespread use of integrated circuits is raising new protection problems, especially in the field of computerized money systems with bank cards that use a single microcircuit for all electronic functions. There is therefore no longer any electronic environment possible that could enable external protection of the integrated circuit. For example, it is no longer possible to use discrete protection components such as special limiter diodes and non-linear resistors for protection against permanent overloads.
Moreover, for these very same reasons, and also because the new technologies are leading to increasingly fragile circuits, it is necessary to identify all the destructive phenomena and protect the entire integrated circuit (and no longer just certain inputs or outputs) against certain destructive phenomena. It is thus becoming necessary to provide the circuit with totally "intrinsic" protection against both electrostatic discharges and permanent overvoltages, including reversals of polarity, by means of an integrated protection structure.
Usually, for a given type of contact pad, it is sought to identify the problem that arises therein for a particular phenomenon and to resolve it..sup.1 FNT .sup.1 A wide variety of structures have been proposed for electrostatic discharge protection. For example, in French patent application No. 91/11007 filed on behalf of the present Inventor, a voltage follower device is thus placed between the drain and the gate of an output transistor with open drain as a protection device against the electrostatic discharges that affect the gate oxide at the position of the drain. Other proposed structures may be found in U.S. Pat. Nos. 5,032,742 (which includes both a series resistance and shunt diodes on a signal input), 4,882,502, 4,876,584, 4,858,055, 4,736,271, 4,716,302, 4,617,482, 4,580,063, 4,438,352, 4,061,928, 4,057,844, 4,032,800, 3,967,295, 3,947,727, 3,712,995, and 3,673,428, all of which are hereby incorporated by reference.
In the invention, there is proposed a strategy of protection that can be applied simultaneously to every destructive phenomenon. The original approach of the invention consists in modifying the current-voltage input characteristic of each of the contact pads of the integrated circuit with respect to a common electrical node internal to the integrated circuit. Advantageously, the internal electrical node is the electrical node of the semiconductor substrate of the integrated circuit. Whereas the semiconductor substrate is usually short-circuited at a contact pad to an external reference voltage (for example a P type substrate is usually biased to the ground Vss), in the invention the semiconductor substrate is isolated from this contact pad and it is biased internally. This original approach further makes it possible advantageously to resolve the problem of protection against polarity reversals.
The invention therefore provides an integrated circuit made out of a semiconductor substrate with a first type of doping, comprising contact pads for the connection of internal functional nodes to external signals, the integrated circuit having a first internal voltage reference delivered by a contact pad to a first external voltage source, the semiconductor substrate being biased at a second internal reference voltage, wherein a diode is connected between the semiconductor substrate and a contact pad to a second external reference voltage source, and wherein the diode is forward biased in the state of normal bias of the integrated circuit and is reverse biased in the state of reverse bias of the integrated circuit by the second internal voltage reference of the integrated circuit.
In the invention, protection devices are advantageously placed between each of the contact pads and the internally biased substrate and, by this original approach, there is obtained a general protection of the integrated circuit against all the destructive phenomena.
The invention relates to an integrated circuit with a protection device against overvoltages between each of the contact pads and the semiconductor substrate.
The invention also relates to a method for the manufacture of an integrated circuit biased by a first external bias voltage and a second external bias voltage wherein, in a semiconductor substrate with a first type of doping, there is made a diffusion of a second type of doping, the substrate being biased by an internal reference voltage in such a way that the substrate and the diffusion form a forward biased diode in the state of normal bias of the integrated circuit and a reverse biased diode in the state of reverse bias of the integrated circuit.
In one class of embodiments, overvoltage protection of a single polarity (e.g. against positive overvoltages) is provided on all contact pads.
In one class of embodiments, the, electrostatic-discharge-protection device is conveniently merged with the overvoltage protection circuitry.
In one class of embodiments, the electrostatic-discharge-protection device is a lateral bipolar transistor with a relatively high trigger voltage (close to the reverse breakdown voltage of the substrate isolation diode). Thus the ESD protection device will not hamper the working of the device for protection against permanent overloads.
In the sample embodiment of FIG. 1, there is an overvoltage-protection device 10i (including current-limiting resistor plus voltage limiter) between each contact pad Pi and the associated internal electrical node Ni; and, in parallel, between each contact pad Pi and the substrate node N0, there is an electrostatic-discharge-protection device 20i.